1. Field of the Invention
The present invention relates to semiconductor process. More particularly, the present invention relates to a method for reducing the critical dimension (CD) and a semiconductor etching method.
2. Description of Related Art
The metal-oxide semiconductor (MOS) transistor is an essential electronic element in the integrated circuits. Thus, the electrical performance of a MOS transistor will affect the quality of the product. A general approach in raising the electrical performance of a MOS transistor is to reduce the smallest linewidth of the gate to increase the operation speed of the gate. Normally, during the fabrication of the gate, a hard mask layer is first formed on the polysilicon layer. Further using a patterned photoresist layer above the hard mask layer as an etching mask, an etching process is performed on the hard mask layer. The hard mask layer is then used as a mask for etching the polysilicon layer to form the gate. However, confined by the yellow light process, this approach can not be used for further miniaturization of devices to attain the smallest line width for the gate. A present, a method that is not limited by the yellow light process is developed to reduce the critical dimension. FIGS. 1A to 1C are schematic cross-sectional views illustrating a process flow of reducing the critical dimension of a MOS transistor gate, according to the prior art. As shown in FIG. 1A, a substrate 100 is provided. A hard mask layer 102 is formed on the substrate 100. A patterned photoresist layer 104 is further formed on the hard mask layer 102, wherein this patterned photoresist layer 104 has a first line width L1.
Referring to FIG. 1B, the photoresist layer is trimmed, curtailing the photoresist layer 104 to a downsized patterned photoresist layer 104 having a line width L2.
Referring to FIG. 1C, a low etching-rate etching process is performed to remove the hard mask layer 102 not covered by the downsized patterned photoresist layer 104′ to form the patterned hard mask layer 102′. The preliminary manufacturing process of a MOS transistor gate is thereby completed.
However, the photoresist trimming process is not stable. When the etching is too fast, the remaining thickness of the photoresist layer may become insufficient, generating the necking or widening phenomenon. Further, the photoresist layer may not be uniform, causing the gate to have a rough sidewall or twisty line. Ultimately, the shape of the gate and the uniformity of the critical dimension are adversely affected.